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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Octal 3-State Noninverting Buffer/Line Driver/ Line Receiver
High-Performance Silicon-Gate CMOS
The MC54/74HC241A is identical in pinout to the LS241. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This octal noninverting buffer/line driver/line receiver is designed to be used with 3-state memory address drivers, clock drivers, and other sub-oriented systems. The device has noninverted outputs and two output enables. Enable A is active-low and Enable B is active-high. The HC241A is similar in function to the HC244A and HC240A. * * * * * * Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A * Chip Complexity: 134 FETs or 33.5 Equivalent Gates
MC54/74HC241A
J SUFFIX CERAMIC PACKAGE CASE 732-03
1
20
20 1
N SUFFIX PLASTIC PACKAGE CASE 738-03
20 1
DW SUFFIX SOIC PACKAGE CASE 751D-04
ORDERING INFORMATION MC54HCXXXAJ MC74HCXXXAN MC74HCXXXADW Ceramic Plastic SOIC
PIN ASSIGNMENT LOGIC DIAGRAM
2 4 6 8 11 13 15 17 18 16 14 12 9 7 5 3 ENABLE A A1 A1 A2 A3 A4 DATA INPUTS B1 B2 B3 B4 YA1 YA2 YA3 YA4 YB1 YB2 YB3 Inputs YB4 Enable A A L L H L H X NONINVERTING OUTPUTS YB4 A2 YB3 A3 YB2 A4 YB1 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC ENABLE B YA1 B4 YA2 B3 YA3 B2 YA4 B1
FUNCTION TABLE
Output YA L H Z Inputs Enable B B H H L L H X Output YB L H Z
OUTPUT ENABLES
1 ENABLE A 19 ENABLE B
PIN 20 = VCC PIN 10 = GND
Z = high impedance
2/97
(c) Motorola, Inc. 1997
1
REV 7
MC54/74HC241A
III I I I I I I I IIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIII I II I II I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I II I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I II I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I II I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I I I I III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I I II I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I III I I I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I III I I III I IIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIII III II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I I
IIIIIIII I I I I IIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII I I I I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I III I I I IIIIIIIIIIIIIIIIIIIIIII I III I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIII I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS*
Symbol VCC Vin Parameter Value Unit V V V DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) - 0.5 to + 7.0 - 0.5 to VCC + 0.5 - 0.5 to VCC + 0.5 20 35 75 750 500 Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA mA mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic or Ceramic DIP SOIC Package Storage Temperature mW Tstg TL - 65 to + 150 260 300
_C _C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
v
v
Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) (Ceramic DIP)
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C Ceramic DIP: - 10 mW/_C from 100_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol VCC Parameter Min 2.0 0 Max 6.0 Unit V V
DC Supply Voltage (Referenced to GND)
Vin, Vout TA
DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1)
VCC
- 55 0 0 0
+ 125 1000 500 400
_C
ns
tr, tf
VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol VIH
Parameter
Test Conditions
VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 4.5 6.0 3.0 4.5 6.0 2.0 4.5 6.0 3.0 4.5 6.0
- 55 to 25_C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9
v 85_C v 125_C
1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9 2.2 3.7 5.2 0.1 0.1 0.1 0.4 0.4 0.4
Unit V
Minimum High-Level Input Voltage
Vout = VCC - 0.1 V |Iout| 20 A
v v v
VIL
Maximum Low-Level Input Voltage
Vout = 0.1 V |Iout| 20 A
V
VOH
Minimum High-Level Output Voltage
Vin = VIH |Iout| 20 A Vin = VIH
V
|Iout| |Iout| |Iout|
v 2.4 mA v 6.0 mA v 7.8 mA v 2.4 mA v 6.0 mA v 7.8 mA
2.48 3.98 5.48 0.1 0.1 0.1
2.34 3.84 5.34 0.1 0.1 0.1
VOL
Maximum Low-Level Output Voltage
Vin = VIL |Iout| 20 A
v
V
Vin = VIL
|Iout| |Iout| |Iout|
0.26 0.26 0.26
0.33 0.33 0.33
MOTOROLA
2
High-Speed CMOS Logic Data DL129 -- Rev 6
MC54/74HC241A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I I I III I I I I IIIIIII IIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIII I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I I
Guaranteed Limit Symbol Iin IOZ Parameter Test Conditions VCC V 6.0 6.0 - 55 to 25_C 0.1 0.5
v 85_C v 125_C
1.0 5.0 1.0 10
Unit A A
Maximum Input Leakage Current Maximum Three-State Leakage Current Maximum Quiescent Supply Current (per Package)
ICC
Vin = VCC or GND Output in High-Impedance State Vin = VIL or VIH Vout = VCC or GND Vin = VCC or GND Iout = 0 A
6.0
4.0
40
160
A
NOTE: Information on typical parametric values along with high frequency or heavy load considerations, can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
II I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I II I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I I II I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I
Guaranteed Limit Symbol S bl tPLH, tPHL Parameter P VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 -- -- - 55 to 25_C 90 45 18 15
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
v 85_C v 125_C
115 60 23 20 135 70 27 23 180 80 36 31 135 80 27 23 90 32 18 15 10 15
Unit Ui ns
Maximum Propagation Delay, Input A to Output Y (Figures 1 and 3)
tPLZ, tPHZ
Maximum Propagation Delay, Output Enable to Y (Figures 2 and 4)
120 60 24 20 90 60 18 15 60 23 12 10 10 15
150 70 30 26 115 70 23 20 75 27 15 13 10 15
ns
tPZL, tPZH
Maximum Propagation Delay, Output Enable to Y (Figures 2 and 4)
ns
tTLH, tTHL
Maximum Output Transition Time, Any Output (Figures 1 and 3)
ns
Cin
Maximum Input Capacitance
pF pF
Cout
Maximum Three-State Output Capacitance (Output in High-Impedance State)
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High- Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V CPD Power Di i i C P Dissipation Capacitance (P T i (Per Transceiver Ch i Channel)* l)* 34 pF F
* Used to determine the no-load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
High-Speed CMOS Logic Data DL129 -- Rev 6
3
MOTOROLA
MC54/74HC241A
SWITCHING WAVEFORMS
VCC ENABLE A tr DATA INPUT A OR B tPLH OUTPUT YA OR YB tTLH 90% 50% 10% tTHL OUTPUT Y 90% 50% 10% tPHL OUTPUT Y tf VCC GND ENABLE B 50% GND tPZL 50% 10% tPZH 50% tPHZ 90% tPLZ HIGH IMPEDANCE VOL VOH HIGH IMPEDANCE 50% GND VCC
Figure 1.
Figure 2.
TEST POINT OUTPUT DEVICE UNDER TEST DEVICE UNDER TEST
TEST POINT OUTPUT 1 k CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH.
CL*
CL*
* Includes all probe and jig capacitance
* Includes all probe and jig capacitance
Figure 3. Test Circuit
Figure 4. Test Circuit
PIN DESCRIPTIONS
INPUTS A1, A2, A3, A4, B1, B2, B3, B4 (Pins 2, 4, 6, 8, 11, 13, 15, 17) Data input pins. Data on these pins appear in noninverted form on the corresponding Y outputs when the outputs are enabled. CONTROLS Enable A (Pin 1) Output enable (active-low). When a low level is applied to this pin, the outputs of the "A" devices are enabled and the devices function as noninverting buffers. When a high level is applied, the outputs assume the high-impedance state. YA1, YA2, YA3, YA4, YB1, YB2, YB3, YB4 (Pins 18, 16, 14, 12, 9, 7, 5, 3) Device outputs. Depending upon the state of the output- enable pins, these outputs are either noninverting outputs or high-impedance outputs. Enable 8 (Pin 19) Output enable (active-high). When a high level is applied to this pin, the outputs of the "B" devices are enabled and the devices function as noninverting buffers. When a low level is applied, the outputs assume the high-impedance state. OUTPUTS
MOTOROLA
4
High-Speed CMOS Logic Data DL129 -- Rev 6
MC54/74HC241A
LOGIC DETAIL
TO THREE OTHER "A" BUFFERS TO THREE OTHER "B" BUFFERS
DATA INPUT A
TWO OF 8 BUFFERS
VCC
YA
DATA INPUT B
VCC
YB
ENABLE A OUTPUT ENABLES ENABLE B
High-Speed CMOS Logic Data DL129 -- Rev 6
5
MOTOROLA
MC54/74HC241A
OUTLINE DIMENSIONS
J SUFFIX CERAMIC PACKAGE CASE 732-03 ISSUE E
B A F C L
DIM A B C D F G H J K L M N NOTES: 1. LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE POSITION AT SEATING PLANE, AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSIONS A AND B INCLUDE MENISCUS. MILLIMETERS MIN MAX 23.88 25.15 6.60 7.49 3.81 5.08 0.38 0.56 1.40 1.65 2.54 BSC 0.51 1.27 0.20 0.30 3.18 4.06 7.62 BSC 0_ 15 _ 0.25 1.02 INCHES MIN MAX 0.940 0.990 0.260 0.295 0.150 0.200 0.015 0.022 0.055 0.065 0.100 BSC 0.020 0.050 0.008 0.012 0.125 0.160 0.300 BSC 0_ 15_ 0.010 0.040
20 1
11 10
N H D
SEATING PLANE
G
K
J M
-A-
20 11
N SUFFIX PLASTIC PACKAGE CASE 738-03 ISSUE E
B
1
10
C
L
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01
-T-
SEATING PLANE
K M E G F D
20 PL
N J 0.25 (0.010)
M 20 PL
0.25 (0.010) TA
M
M
TB
M
DIM A B C D E F G J K L M N
-A-
20 11
DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D-04 ISSUE E
10X
-B-
1 10
P 0.010 (0.25)
M
B
M
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 12.65 12.95 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029
20X
D
M
0.010 (0.25)
TA
S
B
J
S
F R X 45 _ C -T-
18X SEATING PLANE
G
K
M
MOTOROLA
6
High-Speed CMOS Logic Data DL129 -- Rev 6
MC54/74HC241A
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High-Speed CMOS Logic Data DL129 -- Rev 6
7
MC74HC241A/D MOTOROLA

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